SRAM (Static Random Access Memory) devices are well known in the art. A typical SRAM device comprises an array of memory cells with each SRAM cell containing a binary digit (bit) of data. An SRAM cell holds the data in a latch. The latch holds the bit information so long as power is supplied to the cell. Since an SRAM cell can hold the data information indefinitely so long as power is supplied thereto, it can be interrogated either by read or write, at any time. Thus, it is typically an asynchronous device.
However, it is also known in the prior art to provide a single integrated SRAM device with a synchronized write capability. In such a mode of operation, the SRAM device writes only in the presence of a clock signal. Thus its operation is synchronized to that of a clock signal.
Finally, it is known in the prior art to provide an integrated asynchronous SRAM memory array device with discrete logic circuits, i.e. non-single integrated circuit, to provide for burst read, i.e. a single address to the SRAM memory array device causes a plurality of data signals to be read from the SRAM memory array device. However, the use of discrete logic circuits with their inherent delay preclude the use of an SRAM with discrete logic circuits as cache memory devices to processors, with zero wait state.
Another type of prior art single integrated memory device is a DRAM. A DRAM memory device also comprises an array of memory cells. However, each DRAM memory cell stores the data in a capacitor which must be periodically refreshed. This refreshing of the cell of a DRAM device is performed periodically.
However, some DRAM devices do provide the capability of performing a nibble mode read. That is, in a read mode, a DRAM device is capable of supplying on its output a plurality of data bits from a plurality of different cell locations in response to cycling a single input to the DRAM device. Although a single integrated DRAM memory device is capable of performing a nibble mode read, it accomplishes this by dividing the DRAM array into a plurality of subarrays with the same address supplied to each of the subarrays. In this manner, the data from the same address location but from a plurality of different subarrays are read out from the DRAM.
Finally, in part because the SRAM device does not need refreshing, it operates faster than a DRAM device. In addition, a DRAM device uses multiplexed address. Thus, in many applications, such as cache memory, SRAM devices are preferred over DRAM devices because of their speed. As processor speed exceeds that of memory speed, it becomes increasingly desirable to have a cache memory acting as a buffer between the processor and the main memory. The cache memory would have the speed which can keep up with the speed of the processor.